NT3H2211W0FHKH Datasheet, PDF (54/77 Pages) NXP Semiconductors – NTAG I2C plus, NFC Forum Type 2 Tag compliant IC with I2C interface

NXP Semiconductors
NT3H2111/NT3H2211
NFC Forum Type 2 Tag compliant IC with I²C interface
• Page address from 00h to FFh (Sector 1) for NTAG I²C plus 2k
• SRAM buffer addresses when pass-through mode is enabled
Addressing a memory page beyond the limits above results in a NAK response from
NTAG I²C plus.
Pages that are locked against writing cannot be reprogrammed using any write command.
The locking mechanisms include static and dynamic lock bits, as well as the locking of the
configuration pages.
10.11 FAST_WRITE
The FAST_WRITE allows to write data in ACTIVE state to the complete SRAM (64 bytes)
in pass-through mode, and requires the start block address (0xF0), end address (0xFF)
and writes 64 bytes of data into the NTAG I²C plus SRAM. The FAST_WRITE command
is shown in Figure 26 and Table 31.
Table 32 shows the required timing.
NFC device Cmd Start End
Data
NTAG ,,ACK''
5881 μs
NTAG ,,NAK''
CRC
T_ACK
T_NAK
ACK
57 μs
NAK
57 μs
NT3H2111/NT3H2211
Product data sheet
COMPANY PUBLIC
Time out
Fig 27. FAST_WRITE command
T_TimeOut
aaa-021659
Table 33. FAST_WRITE command
Name
Code
Cmd
A6h
START_ADDR F0h
END_ADDR
FFh
Data
-
-
CRC
ACK
see Table 17
NAK
see Table 17
Description
write complete SRAM
start SRAM in pass-through mode
end SRAM in pass-through mode
data
CRC according to Ref. 1
see Section 10.3
see Section 10.3
Length
1 byte
1 byte
1 byte
64 bytes
2 bytes
4 bit
4 bit
Table 34. FAST_WRITE timing
These times exclude the end of communication of the NFC device.
FAST_WRITE
T_ACK/NAK min
n=9^[1]
T_ACK/NAK max
T_TimeOut
[1] Refer to Section 10.2 “Timing”.
T_TimeOut
5 ms
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 3 February 2016
359930
© NXP Semiconductors N.V. 2016. All rights reserved.
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