NT3H2211W0FHKH Datasheet, PDF (38/77 Pages) NXP Semiconductors – NTAG I2C plus, NFC Forum Type 2 Tag compliant IC with I2C interface

NXP Semiconductors
NT3H2111/NT3H2211
NFC Forum Type 2 Tag compliant IC with I²C interface
9. I²C commands
For details about I²C interface refer to Ref. 3.
SCL
SDA
SCL
Start
Condition
SDA
Input
SDA
Change
1
2
3
7
Stop
Condition
8
9
SDA
MSB
Start
Condition
SCL
1
2
3
ACK
7
8
9
SDA
MSB
ACK
Stop
Condition
001aao231
Fig 17. I²C bus protocol
The NTAG I²C plus supports the I²C protocol. This protocol is summarized in Figure 17.
Any device that sends data onto the bus is defined as a transmitter, and any device that
reads the data from the bus is defined as a receiver. The device that controls the data
transfer is known as the “bus master”, and the other as the “slave” device. A data transfer
can only be initiated by the bus master, which will also provide the serial clock for
synchronization. The NTAG I²C plus is always a slave in all communications.
9.1 Start condition
Start is identified by a falling edge of Serial Data (SDA), while Serial Clock (SCL) is stable
in the high state. A Start condition must precede any data transfer command. The NTAG
I²C plus continuously monitors SDA (except during a Write cycle) and SCL for a Start
condition, and will not respond unless one is given.
9.2 Stop condition
Stop is identified by a rising edge of SDA while SCL is stable and driven high. A Stop
condition terminates communication between the NTAG I²C plus and the bus master. A
Stop condition at the end of a Write command triggers the internal Write cycle.
NT3H2111/NT3H2211
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 3 February 2016
359930
© NXP Semiconductors N.V. 2016. All rights reserved.
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