NT3H2211W0FHKH Datasheet, PDF (39/77 Pages) NXP Semiconductors – NTAG I2C plus, NFC Forum Type 2 Tag compliant IC with I2C interface

NXP Semiconductors
NT3H2111/NT3H2211
NFC Forum Type 2 Tag compliant IC with I²C interface
9.3 I²C soft reset and NFC silence feature
With the bit NFCS_I2C_RST_ON_OFF (see Table 13) NTAG I²C plus enables two
features: a soft reset of the I²C sub-system, and NFC silence, in which the NFC
demodulator is disabled.
The I²C soft reset feature interprets an I²C repeated start (no I²C stop in between) as a
command to execute a soft reset of the I²C sub-system. This is useful when heavy bus
interference can cause the I²C interface to get stuck. A drawback of this feature is that
every start symbol then has to be terminated with a Stop, slowing down communication. If
a Stop is forgotten, the I²C interface is cleared and previous communication, if any, is lost.
Consequently when this feature is used, stop conditions after MEMA for READ/WRITE
(see Figure 18) and after REGA for READ/WRITE registers (see Figure 19) shall be send.
The NFC silence feature disables the demodulator. When feature is set, no NFC
commands are received, and no replies are issued to commands that were not fully
received when NFC Silence was set. This feature allows the tag to “disappear” even if it
still is in the reader field. NTAG I²C plus will remain in the ISO state it was in when NFC
silence was enabled, until NFC silence is removed.
The combination of these two features in a single bit means that I²C soft reset is only
active during NFC silence.
9.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it is the bus master or slave device, releases Serial Data (SDA) after sending
eight bits of data. During the ninth clock pulse period, the receiver pulls Serial Data (SDA)
low to acknowledge the receipt of the 9th data bits.
9.5 Data input
During data input, the NTAG I²C plus samples SDA on the rising edge of SCL. For correct
device operation, SDA must be stable during the rising edge of SCL, and the SDA signal
must change only when SCL is driven low.
9.6 Addressing
To start communication between a bus master and the NTAG I²C plus slave device, the
bus master must initiate a Start condition. Following this initiation, the bus master sends
the device address. The NTAG I²C address from I²C consists of a 7-bit device identifier
(see Table 15 for default value).
The 8th bit is the Read/Write bit (RW). This bit is set to 1b for Read and 0b for Write
operations.
If a match occurs on the device address, the NTAG I²C plus gives an acknowledgment on
SDA during the 9th bit time. If the NTAG I²C plus does not match the device select code, it
deselects itself from the bus and clears the register I2C_LOCKED (see Table 12).
Table 15. Default NTAG I²C address from I²C
Device address
b7
b6
b5
b4
Value
1^[1]
0^[1]
1^[1]
0^[1]
R/W
b3
b2
b1
b0
1 ^[1]
0 ^[1]
1 ^[1]
1/0
NT3H2111/NT3H2211
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 3 February 2016
359930
© NXP Semiconductors N.V. 2016. All rights reserved.
39 of 77