NT3H2211W0FHKH Datasheet, PDF (17/77 Pages) NXP Semiconductors – NTAG I2C plus, NFC Forum Type 2 Tag compliant IC with I2C interface

NXP Semiconductors
NT3H2111/NT3H2211
NFC Forum Type 2 Tag compliant IC with I²C interface
8.3.3 EEPROM
The EEPROM is a non-volatile memory that stores the 7 byte UID, the memory lock
conditions, IC configuration information and the 1912 bytes of user memory (888 byte
user memory in case of the NTAG I²C plus 1k version).
Sector 0 memory map looks totally the same for NTAG I²C plus 1k and 2k version, the
only difference is the dynamic lock bit granularity.
NXP introduced with NTAG I²C plus the possibility to split the memory in an open and a
password protected area see Section 8.3.11.
8.3.4 SRAM
For frequently changing data, a volatile memory of 64 bytes with unlimited endurance is
built in. The 64 bytes are mapped in a similar way as done in the EEPROM, i.e., 64 bytes
are seen as 16 pages of 4 bytes from NFC perspective.
The SRAM is only available if the tag is powered via the VCC pin.
The SRAM is located at the end of the memory space and it is always directly accessible
by the I²C host (addresses F8h to FBh). An NFC device cannot access the SRAM
memory in normal mode (i.e., outside the pass-through mode). The SRAM is only
accessible by the NFC device if the SRAM is mirrored onto the EEPROM memory space.
With SRAM mirror enabled (SRAM_MIRROR_ON_OFF = 1b - see Section 11.2), the
SRAM can be mirrored in the User Memory from start page 01h to 74h for access from the
NFC side.
The Memory mirror must be enabled once both interfaces are ON as this feature is
disabled after each POR.
The register SRAM_MIRROR_BLOCK (see Table 14) indicates the address of the first
page of the SRAM buffer. In the case where the SRAM mirror is enabled and the READ
command is addressing blocks where the SRAM mirror is located, the SRAM byte values
will be returned instead of the EEPROM byte values. Similarly, if the tag is not VCC
powered, the SRAM mirror is disabled and reading out the bytes related to the SRAM
mirror position would return the values from the EEPROM.
In the pass-through mode (PTHRU_ON_OFF = 1b - see Section 8.3.12), the SRAM is
mirrored to the fixed address F0h - FFh for NFC access (see Section 11) in the first
memory sector (Sector 0) for NTAG I²C plus.
8.3.5 Serial number (UID)
The unique 7-byte serial number (UID) is programmed into the first 7 bytes of memory
covering page addresses 00h and 01h - see Figure 7. These bytes are programmed and
write protected during production.
UID0 is fixed to the value 04h - the manufacturer ID for NXP Semiconductors in
accordance with ISO/IEC 14443-3.
NT3H2111/NT3H2211
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 3 February 2016
359930
© NXP Semiconductors N.V. 2016. All rights reserved.
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