NT3H2211W0FHKH Datasheet, PDF (42/77 Pages) NXP Semiconductors – NTAG I2C plus, NFC Forum Type 2 Tag compliant IC with I2C interface

NXP Semiconductors
NT3H2111/NT3H2211
NFC Forum Type 2 Tag compliant IC with I²C interface
The READ and WRITE operation handle always 16 bytes to be read or written (one block
- see Table 6)
For the READ operation (see Figure 18), following a Start condition, the bus master/host
sends the NTAG I²C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to
0. The NTAG I²C plus acknowledges this (A), and waits for one address byte (MEMA),
which should correspond to the address of the block of memory (SRAM or EEPROM) that
is intended to be read. The NTAG I²C plus responds to a valid address byte with an
acknowledge (A). A Stop condition can be then issued. Then the host again issues a start
condition followed by the NTAG I²C plus slave address with the Read/Write bit set to 1b.
When I2C_CLOCK_STR is set to 0b, a pause of at least 50 s shall be kept before this
start condition. The NTAG I²C plus acknowledges this (A) and sends the first byte of data
read (D0).The bus master/host acknowledges it (A) and the NTAG I²C plus will
subsequently transmit the following 15 bytes of memory read with an acknowledge from
the host after every byte. After the last byte of memory data has been transmitted by the
NTAG I²C plus, the bus master/host will acknowledge it and issue a Stop condition.
For the WRITE operation (see Figure 18), following a Start condition, the bus master/host
sends the NTAG I²C plus slave address code (SA - 7 bits) with the Read/Write bit (RW)
reset to 0. The NTAG I²C plus acknowledges this (A), and waits for one address byte
(MEMA), which should correspond to the address of the block of memory (SRAM or
EEPROM) that is intended to be written. The NTAG I²C plus responds to a valid address
byte with an acknowledge (A) and, in the case of a WRITE operation, the bus master/host
starts transmitting each 16 bytes (D0...D15) that shall be written at the specified address
with an acknowledge of the NTAG I²C plus after each byte (A). After the last byte
acknowledge from the NTAG I²C plus, the bus master/host issues a Stop condition.
The memory address accessible via the READ and WRITE operations can only
correspond to the EEPROM or SRAM (respectively 00h to 3Ah or F8h to FBh for NTAG
I²C plus 1k and 00h to 7Ah or F8h to FBh for NTAG I²C plus 2k).
NT3H2111/NT3H2211
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 3 February 2016
359930
© NXP Semiconductors N.V. 2016. All rights reserved.
42 of 77