NT3H2211W0FHKH Datasheet, PDF (58/77 Pages) NXP Semiconductors – NTAG I2C plus, NFC Forum Type 2 Tag compliant IC with I2C interface

NXP Semiconductors
NT3H2111/NT3H2211
NFC Forum Type 2 Tag compliant IC with I²C interface
11.2 SRAM buffer mapping with Memory Mirror enabled
With SRAM_MIRROR_ON_OFF= 1b, the SRAM buffer mirroring is enabled. This mode
cannot be combined with the pass-through mode (see Section 11.3).
With the memory mirror enabled, the SRAM is now mapped into the user memory from
the NFC interface perspective using the SRAM mirror lower page address specified in
SRAM_MIRROR_BLOCK byte (Table 13 and Table 14). See Table 37 (NTAG I²C plus 1k)
and Table 38 (NTAG I²C plus 2k) for an illustration of this SRAM memory mapping when
SRAM_MIRROR_BLOCK is set to 01h.
Password protection to this mapped SRAM may be enabled by enabling password
authentication and setting SRAM_PROT bit to 1b.
The tag must be VCC powered to make this mode work, because without VCC, the SRAM
will not be accessible via NFC powered only.
When mapping the SRAM buffer to the user memory, the user shall be aware that all data
written into the SRAM will be lost once the NTAG I²C plus is no longer powered from the
I²C side (as SRAM is a volatile memory).
NT3H2111/NT3H2211
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.0 — 3 February 2016
359930
© NXP Semiconductors N.V. 2016. All rights reserved.
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