TDA8035HN Datasheet, PDF (12/32 Pages) NXP Semiconductors – Smart card interface externally by a resistor bridge

NXP Semiconductors
TDA8035HN
Smart card interface
8.5 CS control
The CS (Chip Select) input allows multiple devices to operate in parallel. When CS is
high, the system interface signals operate as described. When CS is low , the signals
CMDVCCN, RSTIN, CLKDIV1, CLKDIV2, EN5V/3VN and EN1V8N are latched. I/OUC,
AUX1UC and AUX2UC are set to high impedance pull up mode and won’t pass data to or
from the smart card. OFFN output is tri-stated.
8.6 Shutdown mode and Deep Shutdown mode
After power-on reset, the circuit enters the Shutdown mode if CMDVCCN input pin is to a
logic-High. A minimum number of circuits are active while waiting for the micro-controller
to start a session.
1. All card contacts are inactive (approximately 200 Ω to GND).
2. I/OUC, AUX1UC and AUX2UC are high impedance (10 k pull-up resistor connected
to V_DDI).
3. Voltage generators are stopped.
4. Voltage supervisor is active.
5. The internal oscillator runs at its low frequency.
A Deep Shutdown mode can be entered by forcing CMDVCCN input pin to a logic-High
state and EN5V/3VN, EN1V8N input pins to a logic-Low state. Deep Shutdown mode can
only be entered when the smart card reader is inactive. In Deep Shutdown mode, all
circuits are disabled. The OFFN pin follows the status of PRESN pin. To exit Deep
Shutdown mode, change the state of one or more of the three control pins. Figure 8
shows the control sequence for entering and exiting.
DEACTIVATION
SEQUENCE
CMDVCCN
EN1V8N
EN5V/3VN
Shutdown
Shutdown
Mode
(internal pin)
Activation
Deep Shutdown
OFFN
PRESN
VCC
Fig 7. Shutdown mode and Deep Shutdown mode
Shutdown
debounce
Activation
001aan751
TDA8035HN
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 19 April 2011
© NXP B.V. 2011. All rights reserved.
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