TDA8035HN Datasheet, PDF (11/32 Pages) NXP Semiconductors – Smart card interface externally by a resistor bridge

NXP Semiconductors
TDA8035HN
Smart card interface
8.4 I/O circuitry
The three data lines I/O, AUX1 and AUX2 are identical.
The Idle state is realized by both lines (I/O and I/OUC) being pulled HIGH via a 10 k
resistor (I/O to V_CC and I/OUC to V_DD(INTF)).
I/O is referenced to V_CC, and I/OUC to V_DD(INTF), thus allowing operation with
V_CC ≠ V_DD(INTF).
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables the detection of falling edges on the other line, which becomes a slave.
After a time delay t_d(edge), the logic 0 present on the master side is transmitted to the slave
side.
When the master side returns to logic 1, the slave side transmits the logic 1 during the
time delay tpu, and then both sides return to their Idle states.
This active pull-up feature ensures fast Low to High transitions; it is able to deliver more
than 1 mA up to an output voltage of 0.9 V_CC on a 80 pF load. At the end of the active
pull-up pulse, the output voltage only depends on the internal pull-up resistor, and on the
load current.
The current to/from the cards I/O lines is internally limited to 15 mA.
The maximum frequency on these lines is 1.5 MHz.
TDA8035HN
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 19 April 2011
© NXP B.V. 2011. All rights reserved.
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