NP5Q128A13ESFC0E Datasheet, PDF (49/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Numonyx® Omneo™ P5Q Datasheet
DC and AC parameters
Table 15.
AC characteristics⁽¹⁾
Test conditions specified in Table 10 and Table 12
Symbol Alt.
Parameter
Min
Typ⁽²⁾
Clock frequency for the following instructions: DOFR,
f_C
f_C DIFP, FAST_READ, SE, BE, WREN, WRDI, RDID, D.C.
RDSR, WRSR (0 to +70 ^oC)
f_R
f_C / f_R
t_CH(3)
t_CL(2)
t_CLCH(4)
t_CHCL(4)
t_SLCH
t_CHSL
t_DVCH
t_CHDX
t_CHSH
t_SHCH
t_SHSL
t_SHQZ(4)
t_CLQV
Clock frequency for the following instructions: QOFR,
QIFP (0 to +70 ^oC)
Clock frequency for READ instructions (0 to +70 ^oC)
Clock frequency for ALL instructions: QOFR, QIFR,
DOFR, DIFP, FAST_READ, READ SE, BE, WREN,
WRDI, RDID, RDSR, WRSR (-30 to +85 ^oC)
t_CLH Clock High time
t_CLL Clock Low time
Clock rise time⁽⁵⁾ (peak to peak)
Clock fall time⁽⁵⁾ (peak to peak)
t_CSS S active setup time (relative to C)
S not active hold time (relative to C)
t_DSU Data in setup time
t_DH Data in hold time
S active hold time (relative to C)
S not active setup time (relative to C)
t_CSH S deselect time
t_DIS Output disable time
Clock Low to Output valid under 30 pF
t_V
Clock Low to Output valid under 10 pF
D.C.
D.C.
D.C.
6.5
6.5
0.1
0.1
5
5
2
5
5
5
80
t_CLQX t_HO Output hold time
0
t_HLCH
HOLD setup time (relative to C)
5
t_CHHH
HOLD hold time (relative to C)
5
t_HHCH
HOLD setup time (relative to C)
5
t_CHHL
HOLD hold time (relative to C)
5
t_HHQX(4) t_LZ HOLD to Output Low-Z
t_HLQZ(4) t_HZ HOLD to Output High-Z
t_WHSL(6)
Write protect setup time
20
t_SHWL(6)
Write protect hold time
100
t_RDP(4)
S High to standby mode
Max Unit
66 MHz
50 MHz
33 MHz
33 MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
8 ns
9 ns
8 ns
ns
ns
ns
ns
ns
10 ns
10 ns
ns
ns
30 µs
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