NP5Q128A13ESFC0E Datasheet, PDF (11/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Numonyx® Omneo™ P5Q Datasheet
Signal descriptions
2.5
Hold (HOLD/DQ3)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the hold condition, the serial data output (DQ1) is high impedance, and serial data
input (DQ0) and Serial Clock (C) are don’t care.
To start the hold condition, the device must be selected, with Chip Select (S) driven Low.
During the quad input fast program (QIFP) instruction, this pin is used for data input (DQ3).
It is latched on the rising edge of the Serial Clock (C).
During the quad output fast read (QOFR) instructions, this pin is used for data output (DQ3).
Data is shifted out on the falling edge of Serial Clock (C).
2.6
Write protect (W/DQ2)
This input signal is used to freeze the size of the area of memory that is protected against
program or erase instructions (as specified by the values in the BP3, BP2, BP1 and BP0 bits
of the status register).
During the quad input fast program (QIFP) instruction, this pin is used for data input (DQ2).
It is latched on the rising edge of the Serial Clock (C).
During the quad output fast read (QOFR) instructions, this pin is used for data output (DQ2).
Data is shifted out on the falling edge of Serial Clock (C).
2.7
V_CC supply voltage
V_CC is the supply voltage.
2.8
V_SS ground
V_SS is the reference for the V_CC supply voltage.
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