NP5Q128A13ESFC0E Datasheet, PDF (25/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Numonyx® Omneo™ P5Q Datasheet
Instructions
6.2
Write disable (WRDI)
The write disable (WRDI) instruction (Figure 7) resets the write enable latch (WEL) bit.
The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The write enable latch (WEL) bit is reset under the following conditions:
– Power-up
– Write disable (WRDI) instruction completion
– Write status register (WRSR) instruction completion
– Page program (PP) instruction completion
– Dual input fast program (DIFP) instruction completion
– Quad input fast program (QIFP) instruction completion
– Sector erase (SE) instruction completion
– Bulk erase (BE) instruction completion
Figure 7. Write disable (WRDI) instruction sequence
S
C
DQ0
DQ1
01234567
Instruction
High Impedance
AI13732
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