NP5Q128A13ESFC0E Datasheet, PDF (10/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Signal descriptions
2
Signal descriptions
Numonyx® Omneo™ P5Q Datasheet
2.1
Serial data input (D/DQ0)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
During the dual output fast read (DOFR) and quad output fast read (QOFR) instructions, this
pin is used as an output (DQ0). Data is shifted out on the falling edge of the Serial Clock (C).
2.2
Serial data output (Q/DQ1)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
During the dual input fast program (DIFP) and quad input fast program (QIFP) instructions,
this pin is used for data input (DQ1). It is latched on the rising edge of the Serial Clock (C).
During the dual output fast read (DOFR) and quad output fast read (QOFR) instructions, this
pin is used as data output (DQ1). Data is shifted out on the falling edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data on
serial data output (DQ1) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and serial data output (DQ1) is at
high impedance. Unless an internal program, erase, or write status register cycle is in
progress, the device will be in the standby power mode. Driving Chip Select (S) Low
enables the device, placing it in the active power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
10/56