NP5Q128A13ESFC0E Datasheet, PDF (12/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

SPI modes
3
SPI modes
Numonyx® Omneo™ P5Q Datasheet
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in standby mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus master and memory devices on the SPI bus
R
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDO
SDI
SCK
SPI Bus Master
R
CS3 CS2 CS1
V_SS
V_CC
C
V_CC
DQ1DQ0
V_SS
C
V_CC
DQ1 DQ0
V_SS
C
V_CC
DQ1DQ0
V_SS
SPI memory _R
device
SPI memory _R
device
SPI memory
device
S
W HOLD
S
W HOLD
S
W HOLD
AI13725b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is selected at a time, so only one device drives the serial data output (DQ1) line
at a time, the other devices are high impedance. Resistors R (represented in Figure 3)
ensure that the Omneo™ P5Q PCM is not selected if the bus master leaves the S line in the
high impedance state. As the bus master may enter a state where all inputs/outputs are in
high impedance at the same time (for example, when the bus master is reset), the clock line
(C) must be connected to an external pull-down resistor so that, when all inputs/outputs
become high impedance, the S line is pulled High while the C line is pulled Low (thus
ensuring that S and C do not become High at the same time, and so, that the t_SHCH
requirement is met). The typical value of R is 100 kΩ, assuming that the time constant R*C_p
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