NP5Q128A13ESFC0E Datasheet, PDF (44/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Initial delivery state
Numonyx® Omneo™ P5Q Datasheet
Figure 20. Power-up timing
VCC
VCC(max)
Program, erase and write commands are rejected by the device
Chip selection not allowed
VCC(min)
Reset state
of the
device
VWI
tVSL
Read access allowed
tPUW
Device fully
accessible
Table 8. Power-up timing and V_WI threshold
Symbol
Parameter
t_VSL(1)
t_PUW(1)
V_WI(1)
V_CC(min) to S Low
Time delay to write instruction
Write inhibit voltage
1. These parameters are characterized only.
time
AI04009C
Min Max Unit
100
µs
1
10
ms
1.5
2.5
V
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). The status register contains 00h (all status register bits are 0).
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