NP5Q128A13ESFC0E Datasheet, PDF (43/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Numonyx® Omneo™ P5Q Datasheet
7
Power-up and power-down
Power-up and power-down
At power-up and power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V_CC until V_CC reaches the correct value:
– V_CC(min) at power-up, and then for a further delay of t_VSL
– V_SS at power-down.
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a power on reset
(POR) circuit is included. The logic inside the device is held reset while V_CC is less than the
power on reset (POR) threshold voltage, V_WI – all operations are disabled, and the device
does not respond to any instruction.
Moreover, the device ignores all write enable (WREN), page program (PP), dual input fast
program (DIFP), sector erase (SE), bulk erase (BE), write status register (WRSR)
instructions until a time delay of t_PUW has elapsed after the moment that V_CC rises above
the V_WI threshold. However, the correct operation of the device is not guaranteed if, by this
time, V_CC is still below V_CC(min). No write status register, program, erase instructions
should be sent until the later of:
– t_PUW after V_CC has passed the V_WI threshold
– t_VSL after V_CC has passed the V_CC(min) level.
These values are specified in Table 8.
If the time, t_VSL, has elapsed, after V_CC rises above V_CC(min), the device can be selected
for read instructions even if the t_PUW delay has not yet fully elapsed.
After power-up, the device is in the following state:
– The device is in the standby power mode
– The write enable latch (WEL) bit is reset
– The write in progress (WIP) bit is reset
Normal precautions must be taken for supply line decoupling, to stabilize the V_CC supply.
Each device in a system should have the V_CC line decoupled by a suitable capacitor close
to the package pins (generally, this capacitor is of the order of 100 nF).
At power-down, when V_CC drops from the operating voltage, to below the power on reset
(POR) threshold voltage, V_WI, all operations are disabled and the device does not respond
to any instruction (the designer needs to be aware that if power-down occurs while a write,
program or erase cycle is in progress, some data corruption may result).
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