NP5Q128A13ESFC0E Datasheet, PDF (16/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Operating features
Numonyx® Omneo™ P5Q Datasheet
4.8
4.8.1
Protection modes
There are protocol-related and specific hardware and software protection modes. They are
described below.
Protocol-related protections
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
Omneo™ P5Q PCM features the following data protection mechanisms:
n Power on reset and an internal timer (t_PUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification
n Program, erase, and write status register are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution
n All instructions that modify data must be preceded by a write enable (WREN) instruction
to set the write enable latch (WEL) bit. This bit is returned to its reset state by the following
events:
– Power-up
– Write disable (WRDI) instruction completion
– Write status register (WRSR) instruction completion
– Page program (PP) instruction completion
– Dual input fast program (DIFP) instruction completion
– Quad input fast program (QIFP) instruction completion
– Sector erase (SE) instruction completion
– Bulk erase (BE) instruction completion
n The Block Protect bits (see Section 6.4.3: BP3, BP2, BP1, BP0 bits) and top/bottom bit
(see Section 6.4.4: Top/bottom bit) allow part of the memory to be configured as read-
only. This is the Software Protect Mode (SPM).
n The Write Protect (W) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits,
Top/Bottom (TB) bit and Status Register Write Disable (SRWD) bit to be protected. This
is the Hardware Protected Mode (HPM). For more details, see Section 6.5: Write status
register (WRSR).
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