NP5Q128A13ESFC0E Datasheet, PDF (24/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Instructions
Numonyx® Omneo™ P5Q Datasheet
6.1
Write enable (WREN)
The write enable (WREN) instruction (Figure 6) sets the write enable latch (WEL) bit.
The write enable latch (WEL) bit must be set prior to every page program (PP), dual input
fast program (DIFP), sector erase (SE), bulk erase (BE), write status register (WRSR)
instruction.
The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 6. Write enable (WREN) instruction sequence
S
C
DQ0
DQ1
01234567
Instruction
High Impedance
AI13731
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