NP5Q128A13ESFC0E Datasheet, PDF (22/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Instructions
6
Instructions
Numonyx® Omneo™ P5Q Datasheet
Note:
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial data input DQ0 is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on serial data input DQ0, each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ),
dual output fast read (DOFR), quad output fast read (QOFR), read status register (RDSR) or
read identification (RDID) instruction, the shifted-in instruction sequence is followed by a
data-out sequence. Chip Select (S) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a page program (PP), dual input fast program (DIFP), quad input fast program
(QIFP), sector erase (SE), bulk erase (BE), write status register (WRSR), write enable
(WREN), write disable (WRDI), Chip Select (S) must be driven High exactly at a byte
boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses after Chip Select (S) being driven Low is
an exact multiple of eight.
All attempts to access the memory array during a write status register cycle, program cycle
erase cycle are ignored, and the internal write status register cycle, program cycle, erase
cycle continues unaffected.
Output Hi-Z is defined as the point where data out is no longer driven.
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