NP5Q128A13ESFC0E Datasheet, PDF (34/56 Pages) Numonyx B.V – 128-Mbit, Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface

Instructions
Numonyx® Omneo™ P5Q Datasheet
6.9
Quad output fast read (QOFR)
The quad output fast read (QOFR) instruction is very similar to the read data bytes at higher
speed (FAST_READ) instruction, except that the data are shifted out on four pins (pins
DQ0, DQ1, DQ2 and DQ3) instead of only one. Outputting the data on four pins instead of
one quadruples the data transfer bandwidth compared to the read data bytes at higher
speed (FAST_READ) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the quad
output fast read instruction is followed by a 3-byte address A[23:0] and a dummy byte, each
bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at
that address, are shifted out on DQ0, DQ1, DQ2 and DQ3 at a maximum frequency f_C,
during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on DQ0, DQ1, DQ2 and
DQ3. The whole memory can, therefore, be read with a single quad output fast read
(QOFR) instruction. When the highest address is reached, the address counter rolls over to
00 0000h, so that the read sequence can be continued indefinitely.
Figure 14. Quad output fast read instruction sequence
S
C
Instruction 6Bh
24 bit Address
8 dummy cycles
DQ0
DQ1
Don’t care
Don’t care
DQ2
DQ3
‘1’
Don’t care
1. After 40 clock cycles (cycle labeled 39 in the figured), data inputs (DQi) must be released because they
become outputs.
2. Once 6Bh command is recognized, W and HOLD functionality is automatically disabled.
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