CS4103 Datasheet, PDF (8/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

Signal Definitions (Continued)
Signal
CPS
CTRL0
CTRL1
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DIRECT
GNDA
GNDA
GNDA
GNDA
GNDPLL
GNDVCO
LNKON
LOCKIND
LPS
LREQ
NC
NC
NC
NC
NC
Type
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
GND
GND
GND
GND
GND
GND
O
I/O
I
I
--
--
--
--
--
Table 2-3. Pin Assignment - Sorted Alphabetically
Pin
Pin
No.
Signal
Type No.
Signal
27
NC
4
NC
--
37
--
38
TPA2+
TPB0–
5
NC
7
NC
--
41
--
47
TPB0+
TPB1–
8
NC
10
NC
--
48
--
60
TPB1+
TPB2–
11
NC
--
65
TPB2+
12
NC
13
NC
--
71
--
72
TPBIAS0
TPBIAS1
14
NC
15
NC
--
75
--
18
TPBIAS2
VDD
26
PC0
39
PC1
I
23
I
24
VDD
VDDA
40
PC2
61
R0
I/O
25
--
66
VDDA
VDDA
64
R1
--
67
VDDA
74
RESET#
70
RSVD0
I
78
I
32
VDDIO
VDDIO
22
RSVD0
17
RSVD1
I
33
I
31
VDDPLL
VDDVCO
19
RSVD1
1
SCLK
I
68
O
2
VSS
VSS
3
TPA0–
9
TPA0+
I/O
44
I/O
45
VSSIO
VSSIO
20
TPA1–
I/O
51
XI
30
TPA1+
36
TPA2–
I/O
52
XO
I/O
57
Pin
Type No.
I/O
58
I/O
42
I/O
43
I/O
49
I/O
50
I/O
55
I/O
56
I/O
46
I/O
53
I/O
59
PWR 29
PWR 79
PWR 35
PWR 54
PWR 62
PWR 63
PWR 6
I/O
34
PWR 73
PWR 69
GND 21
GND 80
PWR 16
GND 28
I
76
O
77
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