CS4103 Datasheet, PDF (6/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

Signal Definitions (Continued)
LREQ
1
SCLK
2
NC
3
CTRL0
4
CTRL1
5
VDDIO
6
DATA0
7
DATA1
8
NC
9
DATA2
10
DATA3
11
DATA4
12
DATA5
13
DATA6
14
DATA7
15
VSSIO
16
LOCKIND
17
NC
18
LPS 19
NC
20
Geode™
CS4103
60
NC
59
TPBIAS2
58
TPA2+
57
TPA2–
56
TPB2+
55
TPB2–
54
VDDA
53
TPBIAS1
52
TPA1+
51
TPA1–
50
TPB1+
49
TPB1–
48
NC
47
NC
46
TPBIAS0
45
TPA0+
44
TPA0-
43
TPB0+
42
TPB0-
41
NC
Figure 2-2. Pin Assignment Diagram
Order number: CS4103VHG
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