CS4103 Datasheet, PDF (15/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

Register Descriptions (Continued)
Bit
Name
Address 04h
0
Link_active
1
Contender
2:4
Jitter
5:7
Pwr_class
Address 05h
0
Resume_int
1
ISBR
2
Loop
3
Pwr_fail
4
Timeout
5
Port_event
6
Enab_accel
7
Enab_multi
Address 06h
0:7
RSVD
Address 07h
0:2
Page_select
3
RSVD
4:7
Port_select
Table 3-5. Base Registers (Continued)
Access Reset Description
R/W
1
Link Active: The logical AND of Link_active and LPS active sets the L bit of
the nodes self-ID packet.
R/W
0
Contender: Cleared or set by software to control the value of the C (Con-
tender) bit transmitted in self-ID packet zero.
R
000 Jitter: The difference between the fastest and slowest repeater delay,
expressed as (jitter + 1) * 20ns.
R/W
*
Power Class: Controls the value of the pwr field transmitted in the self_ID
packet. Upon reset, the value of the PC[0:2] strapping pins is loaded into this
field. This field may be subsequently written by software. Power Class is
application dependent (see P1394a specification, Table 8-3).
*Reset value is application dependent.
RW
0
Resume Interrupt Enable: When set to one, the CS4103 sets Port_event to
one if resume operations commence for any port.
RW
0
Initiate short (arbitrated) Bus Reset: When set, an arbitrated short bus
reset will be issued by the CS4103. This bit is self-clearing.
RW
0
Loop Detect: Indicates a loop in the cable topology. A write of one to this bit
clears it to zero. A software clear of this bit will occur if a cable loop is
present.
RW
0
Cable Power Failure Detect: Set to one when the PS bit changes from one
to zero. A write of one to this bit clears it to zero.
RW
0
Arbitration State Machine Timeout: A write of one to this bit clears it to
zero.
RW
0
Port Event Detect: The CS4103 sets this bit to one if any of Connected,
Bias, Disabled or Fault change for a port whose Int_Enable bit is one. The
CS4103 also sets this bit to one if resume operations commence for any port
and Resume_int is one. A write of one to this bit clears it to zero.
RW
0
Enable Arbitration Acceleration: When set, the CS4103 uses the
enhancements specified in clause 7.10. CS4103 behavior is unspecified if
the value of Enab_accel is changed while a bus request is pending.
RW
0
Enable Multi-speed Packet Concatenation: When set, the link signals the
speed of all packets to the CS4103.
--
--
Reserved
RW
000 Page Select: Selects one of eight register pages of which only pages 0, 1,
and 7 are defined. The selected page is accessible at Addresses 08h
through 0Fh.
--
--
Reserved
RW
0000 Port Select: Selects per port information of a register page. If a register
page has per port registers this field selects which port registers are accessi-
ble at Addresses 08h through 0Fh.
Revision 1.0
15
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