CS4103 Datasheet, PDF (5/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

2.0 Signal Definitions
This section defines the signals and external interface of
the CS4103. Figure 2-1 shows the pins organized by their
functional groupings (internal test and electrical pins are
not shown).
2.1 PIN ASSIGNMENT
The tables in this section use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings.
Figure 2-2 on page 6 shows the pin assignment for the
CS4103 with Tables 2-2 and 2-3, on pages 7 and 8, listing
the pin assignments sorted by pin number and alphabeti-
cally by signal name.
Section 2.2 "Signal Descriptions" starting on page 9 pro-
vides a description for each signal within its associated
functional group.
Table 2-1. Pin Type Definitions
Mnemonic
Definition
I
I/O
O
t/s
VDD
VDDIO
VSS
Input Pin
Bidirectional Pin
Output
TRI-STATE Signal
2.5V Core Power Supply
3.3V I/O Power Supply
Ground Connection
Transceiver/
1394 Cable
Connections
TPA[0:2]+
TPA[0:2]–
TBA[0:2]+
TPB[0:2]–
TPBIAS[0:2]
CPS
Power to/from
Bus
PC0
PC1
PC2
Geode™
CS4103
Figure 2-1. Signal Groups
DATA[0:7]
CTRL[0:1]
LREQ
SCLK
LPS
LNKON
DIRECT
LOCKIND
PHY-Link
Interface
XI
XO
RESET#
Clock/Crystal
and
Reset
Connection
Revision 1.0
5
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