CS4103 Datasheet, PDF (14/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

Register Descriptions (Continued)
3.2 BASE REGISTER DESCRIPTIONS
Table 3-4 is a register map of the CS4103’s Base registers. Table 3-5 provides the bit formats for these registers.
Address
00h
01h
02h
03h
04h
05h
06h
07h
Table 3-4. Base Register Bit Map
0
1
RHB
Link_active
Resume_int
IBR
Extended
Max_speed
Contender
ISBR
Page_select
2
3
4
5
6
Physical_ID
R
Gap_count
RSVD
Total_ports
RSVD
Delay
Jitter
Pwr_class
Loop
Pwr_fail
Timeout
Port_event Enab_accel
RSVD
RSVD
Port_select
7
PS
Enab_multi
Bit
Name
Address 00h
0:5
Physical_ID
6
R
7
PS
Address 01h
0
RHB
1
IBR
2:7
Gap_count
Address 02h
0:2
Extended
3
RSVD
4:7
Total_ports
Address 03h
0:2
Max_speed
3
RSVD
4:7
Delay
Access
Table 3-5. Base Registers
Reset Description
R
Undef Physical ID: The CS4103’s node address determined during self-identifica-
tion.
R
Undef Root: Set when the node becomes root.
R
Undef Cable Power Active: This bit is set when cable power is detected above
7.5V. If cable power drops below 7.5V the PS bit will be cleared and the
Pwr_fail bit set.
RW
0
Root Hold-off Bit: When set, the CS4103 will attempt to become root during
the next tree identify process which is subsequent to a bus reset.
RW
0
Initiate Bus Reset: When set, a non-arbitrated long bus reset of 167 µs will
be issued by the CS4103. This bit is self clearing.
RW
3Fh Gap Count: Arbitration gap times are tuned to minimize bus idle time with
this field. Gap times may be optimized for a specific bus configuration. Two
bus resets return gap_count to 3Fh.
R
111 Extended: A value of seven is assigned to this field indicating that the
extended PHY register map has been implemented.
--
--
Reserved
R
1100 Total Ports: This field shows the number of ports implemented by the
CS4103. The CS4103 utilizes three ports.
R
010 Maximum Speed: Indicates CS4103 operational speeds. A value of 010
indicates the CS4103 supports 98.304, 196.608, and 393.216Mbit/sec oper-
ation.
--
--
Reserved
R
0000 Delay: Worst-case repeater delay equals 144 + (delay * 20) ns.
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