CS4103 Datasheet, PDF (12/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

3.0 Register Descriptions
The CS4103 register set consists of Base registers and
selectable Port/Page registers as illustrated in Figure 3-1.
Addresses 00h through 07h access Base registers while
addresses 08h through 0Fh access Port/Page registers.
Port and Page information is selected using the Port_select
and Page_select fields in the Base register at Address 07h.
Of seven possible page addresses, three register pages
are defined: the Port Status page (Page 0), Vendor Identifi-
cation page (Page 1), and Vendor Specific page (Page 7).
Port selection within a page is required for the Port Status
Page. The Vendor Identification page has no per-port infor-
mation and port selection has no effect on addressing this
page. The Vendor Specific page may contain per-port reg-
isters but this implementation does not require port selec-
tion to access user defined registers.
Table 3-1 is a register map of the CS4103 showing the
Base and Port/Page selection registers. The remaining
sub-sections of this chapter provide details on register
access and bit format information.
00h
01h
Base Registers
02h
03h
04h
05h
06h
07h
Port_select
Page_select
08h
09h
Port Status Page
0Ah08h
0Bh09h
0Ch0Ah08h
0Dh0Bh09h
0Eh0Ch0Ah
0Fh _0Dh0Bh
Port Status Page
Port Status Page
Port 0 Page 0
0Eh0Ch
0Fh _0Dh
Port 1 Page 0
0Eh
Port 2 Page 0
0Fh
08h
09h _{Vendor Identification Page}
0Ah
0Bh
0Ch
0Dh
0Eh
Page 1
0Fh
08h
09h _{Vendor Specific Page}
0Ah08h
0Bh09h _{Vendor Specific Page}
0Ch0Ah08h
0Dh0Bh09h
0Eh0Ch0Ah
Vendor Specific Page
Port 0 Page 7
0Fh _0Dh0Bh
0Eh0Ch
0Fh _0Dh
Port 1 Page 7
0Eh
Port 2 Page 7
0Fh
Figure 3-1. Base and Page/Port Registers
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
0
1
RHB
Link_active
Resume_int
IBR
Extended
Max_speed
Contender
ISBR
Page_select
Table 3-1. Register Map
2
3
4
5
6
Physical_ID
R
Gap_count
RSVD
Total_ports
RSVD
Delay
Jitter
Pwr_class
Loop
Pwr_fail
Timeout
Port_event Enab_accel
RSVD
RSVD
Port_select
Page[n], Port[n], Register-0
Page[n], Port[n], Register-1
Page[n], Port[n], Register-2
Page[n], Port[n], Register-3
Page[n], Port[n], Register-4
Page[n], Port[n], Register-5
Page[n], Port[n], Register-6
Page[n], Port[n], Register-7
7
PS
Enab_multi
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