CS4103 Datasheet, PDF (7/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

Signal Definitions (Continued)
Pin
No.
Signal
1 LREQ
2 SCLK
3 NC
4 CTRL0
5 CTRL1
6 VDDIO
7 DATA0
8 DATA1
9 NC
10 DATA2
11 DATA3
12 DATA4
13 DATA5
14 DATA6
15 DATA7
16 VSSIO
17 LOCKIND
18 RSVD NC
19 LPS
20 NC
21 VSS
22 LNKON
23 PC0
24 PC1
25 PC2
26 DIRECT
27 CPS
Table 2-2. Pin Assignment - Sorted by Pin Number
Pin
Pin
Type
No.
Signal
Type
No.
I
28 VSSIO
O
29 VDD
GND
55
PWR
56
--
30 NC
I/O
31 RSVD1
--
57
I
58
I/O
PWR
32 RSVD0
33 RSVD0
I
59
I
60
I/O
34 VDDIO
I/O
61
I/O
35 VDDA
--
36 NC
PWR
62
--
63
I/O
37 NC
I/O
38 NC
--
64
--
65
I/O
39 GNDA
I/O
40 GNDA
GND
66
GND
67
I/O
41 NC
I/O
42 TPB0–
--
68
I/O
69
PWR
43 TPB0+
I/O
70
I/O
44 TPA0–
--
45 TPA0+
I/O
71
I/O
72
I
46 TPBIAS0
I/O
73
--
47 NC
--
74
GND
O
48 NC
49 TPB1–
--
75
I/O
76
I
50 TPB1+
I
51 TPA1–
I/O
77
I/O
78
I/O
52 TPA1+
I/O
79
I
53 TPBIAS1
I/O
80
I
54 VDDA
PWR
Signal
TPB2–
TPB2+
TPA2–
TPA2+
TPBIAS2
NC
GNDA
VDDA
VDDA
GNDA
NC
R0
R1
RSVD1
VDDVCO
GNDVCO
NC
NC
VDDPLL
GNDPLL
NC
XI
XO
RESET#
VDD
VSS
Type
I/O
I/O
I/O
I/O
I/O
--
GND
PWR
PWR
GND
--
--
--
I
PWR
GND
--
--
PWR
GND
--
I
O
I
PWR
GND
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