CS4103 Datasheet, PDF (18/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

Register Descriptions (Continued)
3.5 VENDOR SPECIFIC: PAGE 7, PORTS[0:2]
The Vendor Specific page is reserved for vendor use. It
may contain per-port registers but this implementation
does not require port selection to access user defined reg-
isters. The Vendor Specific page is accessible by setting
the Page_select field in the Base register at Address 07h to
0111b.
Table 3-10. Vendor Specific: Page 7 Bit Map
Address
0
1
2
3
4
5
6
7
08h-0Eh
RSVD
0Fh
RSVD
PD[0]
PD[1]
RSVD
Bits
Name
Addresses 08h-0Eh
0:7
RSVD
Addresses 0Fh
0:2
RSVD
3:4
PD[1:0]
5:7
RSVD
Table 3-11. Vendor Specific: Page 7 Registers
Access Reset Description
Page 7, Port[n], Register-0 through Register-6
RW
00h Reserved: Do not set bits in these fields. Setting bits in these fields may
cause noncompliant or unspecified behavior.
Page 7, Port[n], Register-7
RW
00h Reserved: Do not set bits in these fields. Setting bits in these fields may
cause noncompliant or unspecified behavior.
RW
00
Power Down Mode: The CS4103 will transition to a low power state defined
by these bits when the PHY-Link interface is disabled and the PHY ports are
in the disabled, disconnected or suspended state.
00 = No Power Down.
01 = Stop PLL and 50 MHz clock.
10 = Stop 50 MHz clock.
11 = Stop Crystal, PLL, and 50 MHz clock.
RW
00h Reserved: Do not set bits in these fields. Setting bits in these fields may
cause noncompliant or unspecified behavior.
www.national.com
18
Revision 1.0