CS4103 Datasheet, PDF (21/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

Electrical Characteristics (Continued)
4.4 AC SPECIFICATIONS
Symbol
t_PD1
t_PD2
t_PD3
t_PSU
t_PH
t_R
t_F
Table 4-4. IEEE-1394A PHY-Link Interface Timings
Parameter
Min
Typ
Max Unit
SCLK Frequency
SCLK Duty Cycle
Delay Time, SCLK High to Initial Instance of
DATA[0:7] and CTRL[0:1] Valid
Delay Time, SCLK High to Subsequent
Instances of DATA[0:7] and CTRL[0:1] Valid
Delay Time, SCLK High to DATA[0:7] and
CTRL[0:1] Invalid
Setup Time, DATA[0:7], CTRL[0:1], and
LREQ before SCLK High
Hold Time, DATA[0:7], CTRL[0:1], and
LREQ after SCLK High
Rise Time, DATA[0:7], CTRL[0:1], and SCLK
49.152MHz +/-100ppm
45
55
0.5
13.5
0.5
13.5
0.5
13.5
6
0
0.7
2.4
MHz
%
ns
ns
ns
ns
ns
ns
Fall Time, DATA[0:7], CTRL[0:1], and SCLK
0.7
2.4
ns
Conditions
SCLK
DATA[0:7],
CTRL[0:1]
50%
t_PD1
t_PD2
t_CLK
t_PD3
Figure 4-1. SCLK to Data Valid Timing Waveform
SCLK
DATA[0:7],
CTRL[0:1]
50%
t_PSU
t_PH
Figure 4-2. Setup and Hold Timing Waveform
90%
90%
DATA[0:7],10%
CTRL[0:1],
SCLK
t_R
10%
t_F
Figure 4-3. Rise and Fall Timing Waveforms
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