CS4103 Datasheet, PDF (1/24 Pages) National Semiconductor (TI) – IEEE P1394a Physical Layer Device

July 2000
Geode™ CS4103
IEEE P1394a Physical Layer Device
General Description
The National Semiconductor^® Geode™ CS4103 is a three
port 400 Mbit/sec IEEE 1394 Physical Layer (PHY) device.
The CS4103 complies to revision 2.0 of the P1394a specifi-
cation. The device is a three port implementation of a reus-
able cell design scalable from one to sixteen ports.
The CS4103 supports all of the P1394a enhancements
including connection debounce, arbitrated reset, ack-accel-
erated arbitration, fly-by concatenation, multi-speed packet
concatenation, PHY pinging, priority arbitration, and Sus-
pend/Resume operation. It also implements the standard
PHY-Link interface defined in IEEE specification 1394-1995
and updated in the P1394a specification for direct connec-
tion with the Geode CS4210 IEEE 1394 Open Host Con-
troller Interface (OHCI) device. The interface can operate in
either direct or isolated mode and supports single capacitor
isolation with bus hold inputs.
The CS4103 provides a complete PHY solution including
all bias generation, differential line drivers and receivers,
single ended comparators for speed signaling, speed sig-
naling current sources, bias detect, and connect detect cir-
cuitry per port. It includes data and strobe encoding/
decoding functions as well as a re-time FIFO to synchro-
nize the receive data to the local clock domain. The
CS4103 can receive and respond to all the PHY packet
types defined in revision 2.0 of the P1394a specification. It
also supports Suspend and Resume port states and con-
nect detect functions.
The CS4103 generates the internal clocks and the Link
SCLK (System Clock) based on a 24.576 MHz external
crystal or a 24.576 MHz clock input. The CS4103 operates
from a single 3.3V supply and supports transfers at 98.304,
196.608, and 393.216 Mbit/sec, (usually referred to as 100,
200, and 400 Mbit/sec respectively).
Features

IEEE 1394 Physical Layer Device (PHY) compliant with
revision 2.0 of P1394a including all enhancements

Scalable design from one to sixteen ports

Supports data rates of 100, 200, and 400 Mbit/sec

Single 3.3V supply operation

Internal PLL generates SCLK and all internal clocks
from a single 24.576 MHz crystal or clock

Includes Cable Power Sense comparator for cable
power monitoring

Compatible with the Geode CS4210 OHCI Controller
and other IEEE 1394 OHCI devices

Supports the isolated PHY-Link interface compliant with
1394-1995 and P1394a specifications

Single capacitor bus hold isolation\

Power saving modes

80-pin TQFP (Thin Quad Flat Pack)
System Block Diagram
PCI Bus
EEPROM
I²C Interface
PCI Interface
Geode™ CS4210
IEEE 1394
OHCI Controller
PHY-Link Interface
Geode™ CS4103
P1394a
Physical Layer
IEEE 1394
Cable
Connectors
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