NS486SXF Datasheet, PDF (7/44 Pages) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

1 0 System Overview (Continued)
1 3 5 Interrupt Controller
The NS486SXF interrupt controller consists of two cascad-
ed programmable interrupt controllers that are compatible
with the Intel 8259A Programmable Interrupt Controller
They provide a total of 15 (out of 16) programmable inter-
rupts Three interrupts are reserved for a real time clock-tick
interrupt a real time clock interrupt request and a cascade
interrupt channel The remaining 13 interrupts can be used
by internal or external sources Additional external interrupt
controllers can be cascaded as well
1 3 6 Real Time Clock Calendar
The NS486SXF Real Time Clock Calendar is a low power
clock that provides a time-of-day clock and 100-year calen-
dar with alarm features and battery operation Time is kept
in BCD or binary format It includes 50 bytes of general pur-
pose CMOS RAM and 3 maskable interrupt sources It is
compatible with the DS1287 and MC146818 RTC Calendar
devices except for the general purpose memory size
1 3 7 Power Management Features
The NS486SXF power management structure includes a
number of power saving mechanisms that can be combined
to achieve comprehensive power savings under a variety of
system conditions First of all the core processor power
consumption can be controlled by varying the processor
system clock frequency The internal CPU clock can be di-
vided by 4 8 16 32 or 64 In addition in idle mode the
internal processor clock will be disabled Finally if an exter-
nal crystal oscillator circuit is being used it can be disabled
For maximum power savings all internal clocks can be dis-
abled (except for the real-time clock oscillator)
The clocks of the on-board peripherals can be individually
or globally controlled By setting bits in the power manage-
ment control registers the internal clocks to the DMA con-
troller the ECP port the three-wire interface the timer the
LCD controller the DRAM controller the PCMCIA controller
and the UART can be disabled
In addition to these internal clocks the external SYSCLK
can be disabled via a bit in the power management control
registers
Using various combinations of these power saving controls
with the NS486SXF controller will result in excellent pro-
grammable power management for any application
1 4 NS486SXF SYSTEM BUS
The NS486SXF system bus provides the interface to off-
chip peripherals and memory It offers an ISA-compatible
interface and is therefore capable of directly interfacing to
many ISA peripheral control devices The interface is ac-
complished through the Bus Interface Unit (BIU) The BIU
generates all of the access signals for both internal and
external peripherals and memory Depending upon whether
the access is to internal peripherals external peripherals or
external memory the BIU generates the timing and control
signals to access those resources The BIU is designed to
support a glueless interface to many ISA-type peripherals
For debug purposes the NS486SXF can be set to generate
external bus cycles at the same time as an internal peripher-
al access takes place This gives logic analyzers or other
debug tools the ability to track and capture internal peripher-
al accesses
Access to internal peripherals is accomplished in three CPU
T-states (clock cycles) The fastest access to off-chip I O is
also three T-states When accessing off-chip memory and
I O wait state generation is accomplished through a combi-
nation of NS486SXF chip select logic and off-chip peripher-
al feedback signals
FIGURE 1-2 NS486SXF Internal Busses
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