NS486SXF Datasheet, PDF (30/44 Pages) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

3 0 Device Specifications (Continued)
3 3 3 Ready Feedback Timing Specifications
FIGURE 3-7 Ready Feedback Timing Diagram
TL H 12514 – 16
TABLE 3-7 Ready Signal Timing Specifications
Symbol
Parameter
Formula
Min
Max
t_RACD
t_RDYH
t_RDYI
RDY Active to CMD Rising
(E RDY)T a
0
RDY Hold Time from CMD
0
CMD to RDY Inactive Feedback
1 0T a (Wait)T a
b30
Note The value of (Wait) in the above formulae is the number of programmed wait states associated with that access cycle (default value is 7 but may be
programmed to 0–7) The value of (E RDY) in the above formulae is the number of programmed extended ready states associated with every access cycle
(default number is 2 but may be programmed to 0–2)
3 3 4 OSCX1 AC Specification
FIGURE 3-8 TTL Clock Input Timing Diagram
TL H 12514 – 17
TABLE 3-8 TTL Clock Input Specification
Symbol
Parameter
Min
Max
t_CTp
CTTL Clock Period
40
870
t_CTh
CTTL High Time (Note)
(0 5 X t_CTp) b 4
t_CTl
CTTL Low Time (Note)
(0 5 X t_CTp) b 4
t_CTr
CTTL Rise Time
4
t_CTf
CTTL Fall Time
4
Note Except for the cycle in which the core frequency is changed In this cycle t_CTh and t_CTl relate to different t_CTp cycles
Unit
ns
ns
ns
ns
ns
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