NS486SXF Datasheet, PDF (11/44 Pages) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

2 0 Pin Description Tables (Continued)
TABLE 2-2 DMA Control Pins
Symbol
DRQ 4 DRQ 3
DRQ 2 DRQ 0
DACK 4
DACK 3
DACK 2
DACK 0
TC EOP
Pins
34 32
36 38
35 33
37 39
Type
Function
I DMA ReQuest A DRQn signal requests the internal DMA Controller to transfer data
between the Requesting Device and memory
O DMA ACKnowledge When the CPU has relinquished control of the bus to a requesting DMA
channel the appropriate active-low DACKn signal acknowledges the winning DRQn
40
I O Terminal Count End Of Process This signal may operate either as a terminal count output
or an active-low End of Process input As TC an active-high pulse occurs on this signal when
the terminal count for any DMA channel has been reached As EOP an external device may
terminate the DMA transfer by driving this signal active-low
Symbol
RAS 1 0
CASH 1 0
CASL 1 0
WE
DPH DPL
TABLE 2-3 DRAM Control Pins
Pins Type
Function
30 31 O Row Address Strobe On the falling edge of these active-low signals Bank 1 and Bank 0
respectively should latch in the row address off of SA 12 1 If only one bank of DRAMs are
supported RAS0 will support that bank and RAS1 will be unused
25 26 O Column Address Strobe (High Byte) These active-low signals indicate when the column access is
being made to the high byte of DRAM Bank 1 and DRAM Bank 0 respectively If only one bank of
DRAMs are supported CASH0 will support the high byte of that bank and CASH1 will be unused
28 29 O Column Address Strobe (Low Byte) These active-low signals indicate when the column access is
being made to the low byte of DRAM Bank 1 and DRAM Bank 0 respectively If only one bank of
DRAMs are supported CASL0 will support the low byte of that bank and CASL1 will be unused
23
O Write Enable Active low signal for writing the data into the DRAM bank
1 12
I O DRAM Data Parity DRAM data parity may be enabled or disabled if disabled these two pins will be
unused Otherwise for DRAM writes the NS486SXF’s DRAM Controller will generate odd parity and
drive the odd parity onto these two pins For DRAM reads the NS486SXF’s DRAM Controller will
read the values driven on these two pins and check it for odd parity in association with the
appropriate data byte
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