NS486SXF Datasheet, PDF(33/44 Page) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

NS486SXF Datasheet, PDF (33/44 Pages) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

◁

3 0 Device Specifications (Continued)

3 3 5 3 PARALLEL PORT

TABLE 3-11 Parallel Port Compatibility Mode Handshake Timing Values

Symbol

Measured

From

Measured

Value

(min max)

Compliance

Tready

Tsetup(host)

Tsetup (peripheral)

Tstrobe(host)

Host Output

Peripheral Input

Host Output

Busy VIL

Data Stable

Strobe VOL

Strobe VOH

Strobe VIH

Strobe l VOL

0 min

750 ns min

500 ns max

750 ns min

500 ms max

Compatible Hosts

Compatible Peripherals

Compatible Hosts

Tstrobe (peripheral)

Thold(host)

Thold (peripheral)

Tbusy

Treply

Tack

Peripheral Input

Host Output

Peripheral Input

Peripheral Output

Strobe VIL

Strobe VOH

Strobe VIL

Ack VOL

Strobe l VIL

Data or AutoFd Change

Busy VOH

Ack VOH

Ack VOL

500 ns max

750 ns min

500 ns max

0 min

500 ns min

10 ms max

Compatible Peripherals

Compatible Hosts

Compatible Peripherals

Compliant Peripherals

Compatible Peripherals

Tnbusy

Tnext

Peripheral Output

Host Output

Ack VOH

Ack VIL

Busy VOH

Strobe VOH

0 min

Compliant Peripherals

Compliant Hosts

Note 1 For more information on the history of Centronics Standard Parallel and PC-Compatible Parallel Interfaces see annex Ca and in particular C 6 2 for Busy-

to-Ack timing variations

Note 2 VIL is the low-level voltage input

VOL is the low-level voltage output

VOH is the high-level voltage output

VIH is the high-level voltage input

The maximum value stated for peripherals in this table are referenced to the peripheral For example the peripheral cannot require more than 500 ns data setup

time

Recognize that complementary signal changes may have overlapping signal transistions The zero minimum value cannot be guaranteed

TABLE 3-12 Parallel Port IEEE 1284 Mode Handshake Timing Values

Symbol

TES

TEL

TER

Parameter

Host Response Time

Infinite Response Time

Peripheral Response Time

Peripheral Response Time (ECP Mode Only)

Host Recovery Time (ECP Mode Only)

Minimum Setup or Pulse Width

Minimum Data Setup Time (ECP EPP Modes Only)

Short Response Time (EPP Mode Only)

Long Response Time (EPP Mode Only)

Termination Pulse Width (EPP Mode Only)

Min

35 ms

0 5 ms

50 ms

Max

1 0s

Infinite

35 ms

125 ms

10 ms

Infinite

http www national com

▷