NS486SXF Datasheet, PDF (12/44 Pages) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

2 0 Pin Description Tables (Continued)
TABLE 2-4 Power Pins
Symbol Pins
V_DD
7 17 27
47 63
87 101
131 147
157
V_SS
4 14 24
44 61
84 98
128 144
154
Type
I a5V power to core and I O
I Ground to core and I O
Function
TABLE 2-5 Reset Logic Pins
Symbol Pins Type
Function
RESET
119 O RESET system output driver This active high signal resets or initializes system peripheral logic during
power up or during a low line voltage outage
RESET
120 O Inverse of RESET for peripherals requiring active low reset
PWGOOD 60
I PoWer GOOD This active-high (Schmitt Trigger) input will cause a hardware reset to the NS486SXF
whenever this input goes low This pin will typically be driven by the power supply and PWGOOD will
remain low until the power supply determines that stable and valid voltage levels have been achieved
TABLE 2-6 Auxiliary Processor Interface Pins
Symbol
EREQ CS6 RTS
EACK CS7 DSR
DRV CS8 DTR
Pins
102
103
104
Type
O
IO
I
O
I
O
Function
This pin has three programmable options controlled by the Modem Signal Control Register
(refer to the UART section)
1 External bus REQuest (active-low) to an auxiliary processor
2 Chip Select 6 (active-low) pin
3 Request To Send When low this signal informs the MODEM or data set that the UART is
ready to exchange data The RTS output signal can be set to an active low by programming
bit 2 (RTS) of the MODEM Control Register A Master Reset operation sets this signal to its
inactive (high) state Loop mode operation holds this signal in its inactive state
This pin has three possible programmable options controlled by the Modem Signal Control
Register (refer to the UART section)
1 External bus ACKnowledge (active-low) from an auxiliary processor
2 Chip Select 7 (active-low) pin
3 Data Set Ready When low it indicates that the MODEM or data set is ready to link with the
UART The DSR signal is a MODEM status input whose condition can be tested by the CPU
reading bit 5 (DSR) of the MODEM Status Register Bit 5 is the complement of the DSR
signal Bit 1 (DDSR) of the MODEM Status Register indicates whether the DSR input has
changed state since the previous reading of the MODEM Status Register
Note Whenever the DSR bit of the MODEM Status Register changes state an interrupt is generated if the MODEM
Status Interrupt is enabled
This pin has three possible programmable options controlled by the Modem Signal Control
Register (refer to the UART section)
1 DSP shared memory DRiVe control signal
2 Chip Select 8 (active-low) pin
3 Data Terminal Ready When low this signal informs the MODEM or data set that the UART
is ready to establish a communications link The DTR output signal can be set to an active
low by programming bit 0 (DTR) of the MODEM Control Register to a high level A Master
Reset operation sets this signal to its inactive (high) state Loop mode operation holds this
signal in its inactive state
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