NS486SXF Datasheet, PDF (6/44 Pages) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

1 0 System Overview (Continued)
Certain I O lines not being used by disabled peripherals can
be reconfigured for use as general purpose bidirectional I O
lines (up to 29 pins) This gives the designer maximum flexi-
bility in designing various systems using the NS486SXF de-
vice It is expected that an NS486SXF system will minimally
include the NS486SXF system controller with on-board
processor and I O devices boot ROM and working RAM
memory Many applications will not require any additional
I O support
Finally the NS486SXF implements a very flexible power
management scheme that permits selective control of indi-
vidual I O subsystems with varying levels of power con-
sumption
NS486SXF provides a cost-effective hardware platform for
the design and implementation of a wide range of office
automation and communication systems With its powerful
embedded ‘486-class processor comprehensive set of on-
chip peripheral controllers flexible power management
structure and reconfigurable I O lines NS486SXF makes
possible a variety of end-user systems based on the same
hardware Because of its optimized design and on-board
resources a very cost effective system can be achieved
1 2 32-BIT PROCESSOR CORE
The NS486SXF processor core is an implementation of the
protected mode ‘486 instruction set architecture optimized
using a RISC-like design philosophy for embedded applica-
tions Using this approach the most frequently used instruc-
tions are optimized and on an average execute in a lower
number of clock cycles than a ‘486
The NS486SXF features a three stage pipeline efficient in-
struction prefetching mechanism and single cycle instruc-
tion decoding for most instructions Additionally a 1 kbyte
instruction cache and single cycle DRAM access provide
higher memory performance than a larger unified cache im-
plementation
The NS486SXF processor provides the same programming
model and register set as the standard ‘486 except that real
mode virtual memory and floating point support have been
eliminated These features have little or no impact in em-
bedded applications and save significant silicon real estate
At reset unlike the standard ‘486 the NS486SXF starts up
in protected mode instead of real mode All ‘486 instructions
appropriate to protected mode and our hardware configura-
tion are supported including debug instructions
The NS486SXF is initially available to run 25 MHz at 5V
The processor clock is obtained by dividing the crystal fre-
quency by two For example a 25 MHz NS486SXF runs with
a 50 MHz crystal oscillator as the master clock
As a result of our innovative design the NS486SXF
achieves performance equivalent to a standard ‘486 with
less circuitry This translates into reduced power consump-
tion and a lower overall system cost It also makes the
NS486SXF ideal for ‘‘green’’ systems and battery operated
systems
1 3 SYSTEM SERVICE ELEMENTS
The NS486SXF controller provides the basic hardware re-
sources required for the O S-defined System Service Ele-
ments These include a DRAM controller a DMA controller
programmable interval timer a protected WATCHDOG tim-
er a programmable interrupt controller a real-time clock
and calendar and comprehensive power management fea-
tures
1 3 1 DRAM Controller
The NS486SXF DRAM controller supports one or two ad-
justable-sized banks of dynamic RAM using a 16-bit data
path Support is provided for byte parity (if desired) requir-
ing the DRAM banks to be 18 bits wide when parity is en-
abled Banks can be up to 8 Mbytes in size The DRAM
controller supports page mode read and write operations
and can also support both byte and word accesses All ac-
cess control signals for read write and parity checking are
generated as well as an automatic and programmable CAS-
before-RAS refresh If self-refresh DRAMs are used refresh
can be disabled saving power
NS486SXF provides flexible support for use of a number of
different DRAM configurations using popular DRAM devic-
es Access is optimized for fast page mode DRAMs and
they will provide the highest performance with contiguous
data When accessing data bytes or words in the same
DRAM page the data access is in one cycle This perform-
ance provides fast data access times without the overhead
of a separate data cache Page sizes can be 512 1024
2048 or 4096 bytes Flexibility for DRAM timing is provided
through programming of the DRAM controller registers 3 or
4 cycle page miss accesses and extended CAS cycles can
be selected
Memory bank 0 starts at address 0h memory bank 1 can
start at any address in the 128 Mbyte address map that is a
multiple of its size
1 3 2 DMA Controller
The NS486SXF Direct Memory Access (DMA) controller is a
high speed 16-bit controller that improves system perform-
ance by off-loading from the processor the task of manag-
ing data transfers to and from memory and external devices
Data transfers are done independently from the processor
at a maximum data rate of 2 bytes per 2 clock cycles (A 25
MHz clock yields a 25 megabyte per second transfer rate )
There are six independent DMA channels Requestor and
target addresses have a maximum addressable memory
range of 64 Mbytes Three standard transfer modes single
block and demand are provided giving the designer a wide
range of DMA options A special transfer type cascade-
master allows an external master to access the NS486SXF
ISA-like bus Normal transfers can be from memory to mem-
ory memory to I O and I O to memory DMA transfers are
controlled by DMA control registers in the NS486SXF con-
trol register I O map
1 3 3 Programmable Interval Timer
The NS486SXF programmable interval timer is compatible
with the Intel 8254 programmable interval timer and con-
tains three identical timers (CH0 – CH2) CH0 and CH1 can
be used to generate accurate timing delays under software
control CH2 may be configured to provide a WATCHDOG
timer function
1 3 4 WATCHDOG Timer
The NS486SXF WATCHDOG timer CH2 is a protected
16-bit timer that can be used to prevent system ‘‘lockups or
hangups ’’ It uses a 1 kHz clock generated by the on-chip
real-time clock circuit If the WATCHDOG timer is enabled
and times out a reset or interrupt will be generated allowing
graceful recovery from an unexpected system lockup
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