NS486SXF Datasheet, PDF (17/44 Pages) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

2 0 Pin Description Tables (Continued)
TABLE 2-17 General Purpose Chip Select Pins
Symbol
CS 0
Pins
118
CS 5 1
113 114
115 116
117
Type
Function
O Chip Select 0 This output is used as the chip-select for the system boot ROM It defaults to the
upper 64 kbytes of memory
I O Chip Select 1-5 These pins can be programmed to be either memory or I O mapped chip selects
which are used for glue-less connection to external peripherals When the PCMCIA Controller is
enabled CS 1 and CS 2 become PCMCIA Card Enable outputs 1 and 2 (CE1 and CE2
respectively)
Symbol
REG
ENABLE
DIR
GPI
V_PP SEL2
V_PP SEL1
V_CC SEL
CD RST
CLF
CL2
CL1
LCD 3 0
PD 7 0
Rx
UCLK
CS 4
CS 3
CS 2
CS 1
Pins
1
1
1
1
1
1
1
1
1
1
1
4
8
1
1
1
1
1
1
TABLE 2-18 Summary of Reconfigurable I O Pins
Type
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Pin
79
78
77
72
71
70
69
68
48
50
49
51 52 53 54
81 82 83 85 86 88 89 90
58
59
114
115
116
117
Original Function
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
PCMCIA
LCD
LCD
LCD
LCD
ECP
UART
UART
CS4
CS3
CS2
CS1
Power Up State
TRI-STATE
1
0
TRI-STATE
0
0
1
TRI-STATE
0
0
0
0000
TRI-STATE
TRI-STATE
Oscillating
1
1
1
1
These 29 pins typically used for various I O peripheral purposes as defined in the above tables can be reconfigured for use as
general purpose I O pins if the normally defined I O function is not required
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