NS486SXF Datasheet, PDF (10/44 Pages) National Semiconductor (TI) – NS486TMSXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems

2 0 Pin Description Tables (Continued)
TABLE 2-1 Bus Interface Unit Pins
Symbol
SA 25 0
SD 15 0
SBHE
IOR
IOW
MEMR
MEMW
CS16
RDY
Pins Type
130 132 O
133 134
135 136
137 138
139 140
141 142
143 145
146 148
149 150
151 152
153 155
156 158
159 160
2356 IO
8 9 10
11 13
15 16
18 19
20 21 22
129
O
124
O
125
O
126
O
127
O
122
IO
123
I
Function
System Address bus These output-only signals carry the latched address for the current access
DRAM accesses multiplex the row and column addresses for the DRAMs on the SA 12 1 pins
During Interrupt Acknowledge cycles the internal master interrupt controller’s cascade line
signals CAS 2 0 are driven onto SA 25 23 respectively SA 0 is sampled at the end of reset to
determine if the part will run normally or enter ICE TRI-STATE mode
System Data bus This bi-directional data bus provides the data path for all memory and I O
accesses During transfers with 8-bit devices the upper data byte is not used (SD 15 8 )
Byte High Enable This active-low signal indicates that the high byte (odd address byte) is being
transferred External 16-bit devices should use this signal to help them determine that a data byte
is to be transferred on the upper byte of the System Data bus (SD 15 8 ) 8-bit devices should
ignore this signal SBHE is sampled at the end of power good reset to determine if the boot ROM
is 8- or 16-bit wide
IO Read command This active-low signal instructs an I O device to place data onto the system
data bus
IO Write command This active-low signal indicates to an I O device that a write operation is in
process on the system bus
MEMory Read command This active-low signal instructs a memory mapped device to place data
onto the system data bus
MEMory Write command This active-low signal indicates to a memory mapped device that a write
operation is in process on the system bus
Chip Select 16-bit This active-low feedback signal indicates that the device being accessed is a
16-bit device This signal should be driven by external devices with an open collector driver If a
chip select is programmed to force 16-bit accesses this signal will be asserted (low) during the
access
ReaDY An external device may drive this signal inactive low to insert wait states and extend the
external bus cycle This signal should be driven with an open collector or be TRI-STATE driven
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