SM8211M Datasheet, PDF (9/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

SM8211M
Preamble mode
Preamble mode is a continuous 544-bit long period.
If neither a preamble pattern, rate error nor sync code
is detected during this period, operation transfers to
idle mode.
If a preamble pattern is detected, the preamble mode
544-bit long period is recommenced.
If a rate error is detected, device operation transfers
to idle mode. (A single error occurs when two active
edges occur in the received signal on SIG-IN within
1-bit unit time. A rate error occurs when the number
of errors in the error counter equals the error thresh-
old set by flags ER0 to ER2. The error counter is
reset when a preamble pattern is detected.)
If the sync code is detected, SYN-VAL goes HIGH
and operation transfers to lock mode. (If an error of 2
bits or less occurs, the detected word is recognized as
the sync code.)
Idle mode
In idle mode, a check is made for the presence of a
preamble signal when the RF intermittent-duty con-
trol signals (BS1, BS2, BS3) for battery saving are
active. If a preamble pattern is detected, operation
immediately transfers to preamble mode. If a pream-
ble pattern is not detected, intermittent-duty opera-
tion continues.
A preamble pattern is detected when either a 101010
or 010101 6-bit pattern is detected. Since there is a
reasonable probability that this simple pattern can
occur during a valid communicated signal (data, not
preamble), this 6-bit pattern makes returning to pre-
amble mode easier. This is useful for cases where
weak electric fields, noise or other temporary inter-
ference cause device operation to transfer to idle
mode. Further, if a sync code is detected within one
cycle after device operation has transferred from
lock mode, device operation returns to lock mode. (If
flag BS2 is 0, pin BS2 does not go HIGH during the
cycle after device operation has transferred from
lock mode.)
BS1
BS2
(BS2 flag = 0)
BS2
(BS2 flag = 1)
BS3
62.5 ms
(26.7 ms)
Receive timing
1.953 x N ms
(0.833 x N ms)
1.953 x M ms
(0.833 x M ms)
1062.5 ms (453.3 ms)
Figure 4. Idle mode timing
Error bit
Preamble signal ... 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ...
Preamble count starts
X ^Counting
Preamble count restarts
Preamble detected
Count reset to 0
Figure 5. Preamble pattern sequence
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