SM8211M Datasheet, PDF (14/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

SM8211M
Table 10. Frame number flags
FF2
FF1
FF0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Frame number
0
1
2
3
4
5
6
7
Table 13. Rate error detection set flags
ER2
ER1
ER0 Rate error threshold
0
0
0
Count = 1
0
0
1
Count = 2
0
1
0
Count = 3
0
1
1
Count = 4
1
0
0
Count = 5
1
0
1
Count = 6
1
1
0
Count = 7
1
1
1
Count = 8
Table 11. PLL setup time flags/BS1 rising-edge
setup time flags¹
PL5 PL4 PL3 PL2 PL1 PL0
(RF5) (RF4) (RF3) (RF2) (RF1) (RF0)
PLL setup time
(BS1 rising-edge setup
time)
LBO = 0
LBO = 1
0 0 0 0 0 0 0.000 ms 0.000 ms
0 0 0 0 0 1 0.833 ms 1.953 ms
0 0 0 0 1 0 1.667 ms 3.906 ms
↓↓↓↓↓↓
↓
↓
0 1 1 1 1 1 25.833 ms 60.547 ms
1 0 0 0 0 0 26.667 ms 62.500 ms
1 0 0 0 0 1 27.500 ms 64.453 ms
↓↓↓↓↓↓
↓
↓
1 1 1 1 0 1 50.833 ms 119.141 ms
1. Note that (BS3 rising-edge setup time) − (BS1 rising-edge setup
time) should be ≥ 2.
Table 12. Digital filter constant set flags¹
FL2
FL1
0
×
1
0
1
0
1
1
1
1
1. × = don’t care
FL0
Filter constant
×
Digital filter not used
0
Filter constant 1
1
Filter constant 2
0
Filter constant 3
1
Filter constant 4
NIPPON PRECISION CIRCUITS—14