SM8211M Datasheet, PDF (16/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

SM8211M
When an address is detected, the next 32-bit data
code word is received. The BCH(31,21) format error
check bits are checked and if a 1-bit or two consecu-
tive bit errors occur, they are corrected. Two random
bit errors, or three or more bit errors are not cor-
rected. If the corrected data MSB is 1, the data is rec-
ognized as a message, data reception continues and
the corrected message data and error check flags are
sent to the CPU. If the MSB is 0, the data is recog-
nized as an address signal or idle code and data
reception or data transmission to the CPU is halted.
Received message codeword
1 codeword
Internal bit
clock
27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1
RX-CLK
20-bit error-corrected message data
RX-DATA
E0 E1 PE
Figure 9. Received message transmit timing
Table 15. Error count flags
E0
E1
Error count
0
0
No errors
1
0
1-bit error
0
1
Two consecutive bit errors
1
1
Two random, or three or more
bit errors
Table 16. Parity check flag
PE
Even-parity check result¹
0
No errors
1
An error occurred
1. The even-parity check is performed on the data before error correction.
CPU Interface
SYN-VAL
If a sync code is detected with two bit errors or less
during sync code detection timing while in preamble,
lock or idle mode, SYN-VAL goes HIGH for the
duration of the next batch (544 bits long).
ADD-DET
If frame data is received and recognized with two bit
errors or less while in lock mode, ADD-DET goes
HIGH for the duration of the next code word period.
If an address is detected in the second code word in
the frame, ADD-DET stays HIGH for the duration of
two code word periods.
BREAK
On a rising edge of BREAK, message reception and
received message transmission are halted. After a
BREAK interrupt, the device waits for frame address
detection or sync code detection timing. This func-
tion is useful in cases of continuing message recep-
tion, because without sync code or other detection
taking place the received data would be deemed to
have many errors.
NIPPON PRECISION CIRCUITS—16