SM8211M Datasheet, PDF (2/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

BLOCK DIAGRAM
SM8211M
XT
XTN
TX-CLK
TX-DATA
SIG-IN
RST
BACKUP BREAK
BS1
BS2
BS3
Timing control
Flag register
Address register
Receive data register
Digital PLL
Data comparator
Preamble pattern
Sync code
Idle code
Error correction
RX-CLK
ADD-DET
SYN-VAL
RX-DATA
VDD
XVDD
VSS
TEST1
TEST2
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
XVDD
BS1
BS2
BS3
VDD
TEST1
TEST2
TX-CLK
TX-DATA
BREAK
RST
RX-DATA
BACKUP
SIG-IN
VSS
ADD-DET
RX-CLK
SYN-VAL
XT
XTN
I/O
Description
–
Oscillator circuit supply pin. Capacitor connected between XVDD and VSS.
O
RF control main output signal
O
RF DC-level adustment signal
O
PLL setup signal
–
Supply voltage
I
Test pin. Leave open for normal operation.
I
Test pin. Leave open for normal operation.
I
ID data read sync clock
I
ID data input
I
Message transmission interrupt
I
Hardware reset input
O
Received data output (to CPU)
I
Power save
I
NRZ signal input pin
–
Ground
O
Address detection output. HIGH on detection
O
Received data output sync clock
O
Sync code detection output. HIGH on detection
I
76.8 or 153.6 kHz oscillator or external clock input pin
O
Oscillator output pin
I:Input O:Output
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