SM8211M Datasheet, PDF (1/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

NIPPON PRECISION CIRCUITS INC.
SM8211M
POCSAG Decoder For Pagers
OVERVIEW
The SM8211M is a POCSAG-standard (Post Office
Code Standardization Advisory Group) signal pro-
cessor LSI, which conforms to CCIR recommenda-
tion 584 concerning standard international wireless
calling codes.
The SM8211M supports call messages in either tone,
numerical or character outputs at signal speeds of
512 bps or 1200 bps using a 76.8 kHz system clock,
or 2400 bps using a double-speed 153.6 kHz system
clock. Note that output timing values for 2400 bps
mode operation are not shown in this datasheet, but
can be obtained by halving the values for 1200 bps
mode operation.
CMOS structure and low-voltage operation realize
low power dissipation, plus an intermittent-duty
receive method (battery-saving function) reduces
battery consumption.
The SM8211M is available in 20-pin SSOPs.
FEATURES
s Conforms to POCSAG standard for pagers
s 512 or 1200 bps signal speed
s Supports tone, numeric or character call messages
s Battery-saving function for low battery consump-
tion
s BS1 (RF control main output signal) and BS3
(PLL setup signal) 60-step setup time setting—for
BS3, 50.8 ms (max) at 1200 bps and 119.1 ms
(max) at 512 bps
Note that (BS3 setup time) − (BS1 setup time)
should be set to ≥ 2.
s BS2 (RF DC-level adjustment signal) before/dur-
ing reception selectable adjustment timing
s 6 addresses × 4 sub-addresses (total of 24
addresses)
s 1-bit and 2-bit burst error auto-correction function
(messages only)
s 25 to 75% duty factor signal coverage (during pre-
amble detection)
s 8 rate error detection condition settings
s 8 receive mode settings
s 76.8 or 153.6 kHz system clock (crystal oscillator
or external clock input)
s Built-in oscillator capacitor
s Built-in input signal filter, with filter ON/OFF and
4 selectable filter characteristics
s 1.2 to 3.5 V (76.8 kHz system clock) or 2.0 to 3.5
V (153.6 kHz system clock) operating supply volt-
age
s Molybdenum-gate CMOS process realizes low
power dissipation
s 20-pin SSOP
PINOUT
XVDD 1
BS1 2
BS2 3
BS3 4
VDD 5
TEST1 6
TEST2 7
TX-CLK 8
TX-DATA 9
BREAK 10
20 XTN
19 XT
18 SYN-VAL
17 RX-CLK
16 ADD-DET
15 VSS
14 SIG-IN
13 BACKUP
12 RX-DATA
11 RST
PACKAGE DIMENSIONS
7.40max
7.20 0.05
0.20 0.05
2.35
0.65 0.12
44
0.68 0.12
0.30 0.15
NIPPON PRECISION CIRCUITS—1