SM8211M Datasheet, PDF (17/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

SM8211M
Extended Reset
When RST goes LOW for 1 to 2 ms or longer, BS1
and BS3 together go HIGH. Approximately 1 to 2 ms
after RST goes HIGH, device operation continues.
When RST is LOW for less than 200 ms
This function is useful for checking the RF stage cir-
cuits. After RST goes HIGH, the device waits for the
ID code input.
RST
BS1
1 to 2 ms
1 to 2 ms
BS3
Figure 10. Extended reset timing
When RST is LOW for more than 200 ms
If the RST LOW-level pulsewidth exceeds 200 ms,
the parameters for switch-ON mode should be
quickly set over again as soon as RST returns HIGH.
> 200 ms
1 to 200 ms
RST
TX-CLK
TX-DATA
DATA
BS1
BS3
BS3 can also follow the dashed line during this interval.
Figure 11. Extended reset timing (≥ 200 ms)
For internal oscillator operation, RST goes LOW for
1 ms or longer immediately after power is applied or
just after a BACKUP release. After RST returns
HIGH, a wait time of approximately 900 ms (V_DD =
1.5 to 3.5 V) or 1.5 s (V_DD < 1.5 V) should be
observed before operation starts.
NIPPON PRECISION CIRCUITS—17