SM8211M Datasheet, PDF (18/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

SM8211M
Power Save Control
When BACKUP goes LOW, the internal operation
stops and all outputs go high impedance. When
power save mode is released for normal operation,
switch-ON mode internal initialization and ID code
re-setting is required. The XT clock and TX-CLK
timing when BACKUP goes LOW is described
below.
TX-DATA loading
During TX-DATA loading, TX-CLK should be
maintained and not stopped until the ID code is read
in.
Also, the XT clock should be maintained until after
the equivalent time of 1 bit after the ID code is read
in (150 cycles at 512 bps and 64 cycles at 1200 bps).
RST
XT
TX-CLK
BACKUP
1 bit equivalent time
BACKUP
ENABLE
(internal)
Figure 12. TX-DATA load timing
TX-DATA when not loading
System Clock
After BACKUP has gone LOW, the XT clock should
be maintained for the equivalent time of 65 bits or
longer.
The SM8211M operates using a 76.8 or 153.6 kHz
system clock. The clock can be set up using a crystal
oscillator or an externally input clock.
Input Signal Digital Processing (Digital
Filter)
In pagers, two baud rates, 512 and 1200 bps, are in
use. The current method of ensuring the most suit-
able reception conditions is to substitute RF-stage
LPF constants that are proportional to the baud rate.
In the SM8211M, digital processing of the signal
input deals with both baud rates without substituting
RF-stage LPF constants. With this digital processing,
a particularly small rise in the rate error probability
can be expected.
For crystal oscillator clocks, only a crystal needs to
be connected between XT and XTN. The oscillator
amplifier, feedback resistor and oscillator capacitor
are all built-in.
For externally input clocks, the clock is connected to
XT through a 100 pF to 0.1 µF coupling capacitor.
In both cases, crystal oscillator and external clock, a
supply decoupling capacitor of 1000 pF to 0.1 µF
should be connected between XVDD and VSS. Also,
the output on XTN should not be used as a clock to
drive an external device.
The digital processing can be set ON or OFF using
flag FL2, and when ON, there are four filter constant
settings that can be set using flags FL0 and FL1 to
obtain the most suitable reception conditions in a
flexible manner. (See table 12.)
NIPPON PRECISION CIRCUITS—18