SM8211M Datasheet, PDF (15/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

SM8211M
Received Data Transmission (SM8211M to CPU)
In lock mode, if the receive data for the frame is rec-
ognized as one of the 24 addresses with 2 bit errors
or less, then ADD-DET goes HIGH for the duration
of the next code word period and the corresponding
5-bit address information is transmitted to the CPU
on RX-DATA in sync with RX-CLK.
Detected address codeword
1 codeword
Internal bit
clock
27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1
RX-CLK
RX-DATA
A0 A1 A2 A3 A4
ADD-DET
Figure 8. Received address transmit timing
Table 14. Address set flags
A0 A1 A2 A3 A4
00100
10100
01100
11100
00010
10010
01010
11010
00110
10110
01110
11110
Address
A
B
C
Function
A call
B call
C call
D call
A call
B call
C call
D call
A call
B call
C call
D call
A0 A1 A2 A3 A4
00001
10001
01001
11001
00101
10101
01101
11101
00011
10011
01011
11011
Address
D
E
F
Function
A call
B call
C call
D call
A call
B call
C call
D call
A call
B call
C call
D call
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