SM8211M Datasheet, PDF (6/22 Pages) Nippon Precision Circuits Inc – POCSAG Decoder For Pagers

SM8211M
Code words (address and message signals)
Each code word comprises 32 bits as shown in table 2.
Table 2. Code word format
Code word
Address signal
1 (MSB)¹
2 to 19²
Bit number
20, 21²
Function bits
20 21
Function
0
Address bits
0
0
0
1
A call
B call
1
0
C call
1
1
D call
22 to 31³
32 (LSB)⁴
Check bits Even-parity bit
Message signal
1
Message bits
Check bits Even-parity bit
1. The MSB is the address/message code word control bit. It is 0 for an address signal, and 1 for a message signal.
2. Bits 2 to 21 contain the address or message information.
3. Bits 22 to 31 are BCH(31,21) format generated check bits, where BCH(n,k) = BCH(word length, number of information bits).
4. The LSB is an even-parity bit for bits 1 to 31.
Call number to call sign conversion
This conversion expands a 7-digit decimal call num-
ber into a 21-bit binary call sign, as shown in figure
2.
After expansion, the high-order 18 bits are assigned
to bits 2 to 19 (address signal), and the low-order 3
bits are the user-defined frame identification pattern,
which is stored in ID-ROM. The two function bits
define which of four call functions is active.
7-digit decimal call
1
2
3
4
5
6
7
signal (gap code)
MSB
LSB
21-bit binary 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
conversion
Call sign
1
Bits 2 to 19 (18 bits)
20 21
Frame
identificaton
pattern
Bits 22 to 31 (10 bits)
32
Flag:
0 = address signal
1 = message signal
Function bits
BCH(31,21) generated check bits
Figure 2. Call number to call sign conversion
Even-parity bit
(for bits 1 to 31)
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