UPD784020 Datasheet, PDF (70/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCOMPUTER

mPD784020, 784021
OTHER OPERATIONS
Parameter
NMI low-level width
NMI high-level width
INTP0 low-level width
INTP0 high-level width
INTP1-INTP3 and CI low-
level width
INTP1-INTP3 and CI high-
level width
INTP4 and INTP5 low-level
width
INTP4 and INTP5 high-level
width
RESET low-level width
RESET high-level width
Symbol
tWNIL
tWNIH
tWIT0L
tWIT0H
tWIT1L
tWIT1H
tWIT2L
tWIT2H
tWRSL
tWRSH
Conditions
Min.
10
10
3tCYSMP + 10
3tCYSMP + 10
3tCYCPU + 10
3tCYCPU + 10
10
10
10
10
Max.
Unit
ms
ms
ns
ns
ns
ns
ms
ms
ms
ms
Remark tCYSMP: sampling clock specified using software
tCYCPU: CPU operating clock specified using CPU software
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 3.4 to 5.5 V, +3.4 V £ AVREF1 £ AVDD,
VSS = AVSS = 0 V)
Parameter
Resolution
Total error^Note
Linearity calibration^Note
Quantization error
Conversion time
Sampling time
Analog input voltage
Analog input impedance
AVREF1 current
AVDD supply current
Symbol
Conditions
VDD = AVDD = +5.0 V ±10 %
+3.4 V £ AVREF1 £ AVDD
+2.7 V £ VDD = AVDD £ +3.3 V
+2.5 V £ AVREF1 £ AVDD
tCONV tCYK £ 500 ns, FR = 1
tCYK £ 500 ns, FR = 0
tSAMP tCYK £ 500 ns, FR = 1
tCYK £ 500 ns, FR = 0
VIAN
RAN
AIREF1
AIDD1 fXX = 25 MHz
AIDD2 STOP mode, CS = 0
Min.
Typ.
Max.
Unit
8
bit
1.2
%
1.0
%
1.0
%
120
180
24
36
–0.3
0.6
±1/2
1000
0.5
2.0
AVREF1 + 0.3
1.5
5.0
20
%
LSB
tCYK
tCYK
tCYK
tCYK
V
MW
mA
mA
mA
Note Quantization error is excluded. The error is represented in percent with respect to a full-scale value.
Remark tCYK: system clock cycle time
70