UPD784020 Datasheet, PDF (45/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCOMPUTER

mPD784020, 784021
9.2 VECTORED INTERRUPT
When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt
source is used as the branch address.
Interrupt handling by the CPU consists of the following operations :
• When a branch occurs : Push the CPU status (PC and PSW contents) to the stack.
• When control is returned: Pop the CPU status (PC and PSW contents) from the stack.
To return control from the handling routine to the main routine, use the RETI instruction. The branch destination
addresses must be within the range of 0 to FFFFH.
Table 9-3 Vector Table Address
Interrupt source
BRK instruction
Operand error
NMI
WDT
INTP0
INTP1
INTP2
INTP3
INTC00
INTC01
INTC10
INTC11
INTC20
INTC21
INTC30
INTP4
INTP5
INTAD
INTSER
INTSR
INTCSI1
INTST
INTCSI
INTSER2
INTSR2
INTCSI2
INTST2
Vector table address
003EH
003CH
0002H
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0024H
0026H
0028H
002AH
002CH
002EH
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