UPD784020 Datasheet, PDF (67/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCOMPUTER

(3) External wait timing
Parameter
Symbol
Conditions
Address Æ WAITØ input time tDAWT VDD = +5.0 V ±10 %
ASTBØ Æ WAITØ input time tDSTWT VDD = +5.0 V ±10 %
ASTBØ Æ WAIT hold time
tHSTWTH VDD = +5.0 V ±10 %
ASTBØ Æ WAIT• delay time tDSTWTH VDD = +5.0 V ±10 %
RDØ Æ WAITØ input time
tDRWTL VDD = +5.0 V ±10 %
RDØ Æ WAITØ hold time
tHRWT VDD = +5.0 V ±10 %
RDØ Æ WAIT• delay time
tDRWTH VDD = +5.0 V ±10 %
WAIT• Æ data input time
tDWTID VDD = +5.0 V ±10 %
WAIT• Æ WR• delay time
WAIT• Æ RD• delay time
WRØ Æ WAITØ input time
tDWTW
tDWTR
tDWWTL VDD = +5.0 V ±10 %
WRØ Æ WAIT hold time
tHWWT VDD = +5.0 V ±10 %
WRØ Æ WAIT• delay time
tDWWTH VDD = +5.0 V ±10 %
Remark T: TCYK (system clock cycle time)
a: 1 when address wait is applied, 0 in other cases
n: number of wait cycles (n • 0)
(4) Refresh timing
Parameter
Symbol
Conditions
Random read/write cycle time tRC
REFRQ low-level pulse width tWRFQL VDD = +5.0 V ±10 %
ASTBØ Æ REFRQ delay time tDSTRFQ
RD• Æ REFRQ delay time
tDRRFQ
WR• Æ REFRQ delay time tDWRFQ
REFRQ• Æ ASTB delay time tDRFQST
REFRQ high-level pulse width tWRFQH VDD = +5.0 V ±10 %
Remark T: TCYK (system clock cycle time)
mPD784020, 784021
Min.
Max.
Unit
(2 + a) T – 40 ns
(2 + a) T – 60 ns
1.5T – 40
ns
1.5T – 60
ns
(0.5 + n) T + 5
ns
(0.5 + n) T + 10
ns
(1.5 + n) T – 40 ns
(1.5 + n) T – 60 ns
T – 50
ns
T – 70
ns
nT + 5
ns
nT + 10
ns
(1 + n) T – 40 ns
(1 + n) T – 60 ns
0.5T – 5
ns
0.5T – 10
ns
0.5T
ns
0.5T
ns
T – 50
ns
T – 75
ns
nT + 5
ns
nT + 10
ns
(1 + n) T – 40 ns
(1 + n) T – 60 ns
Min.
Max.
Unit
3T
ns
1.5T – 25
ns
1.5T – 30
ns
0.5T – 9
ns
1.5T – 9
ns
1.5T – 9
ns
0.5T – 9
ns
1.5T – 25
ns
1.5T – 30
ns
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