UPD784020 Datasheet, PDF (65/90 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCOMPUTER

mPD784020, 784021
AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Conditions
Min.
Max.
Unit
Address setup time
tSAST VDD = +5.0 V ±10 %
(0.5 + a) T – 11
ns
(0.5 + a) T – 15
ns
ASTB high-level width
tWSTH VDD = +5.0 V ±10 %
(0.5 + a) T – 17
ns
(0.5 + a) T – 40
ns
Address hold time
tHSTLA VDD = +5.0 V ±10 %
0.5T – 24
ns
(referred to ASTBØ)
0.5T – 34
ns
Address hold time
tHRA
0.5T – 14
ns
(referred to RD•)
Address Æ RDØ delay time tDAR VDD = +5.0 V ±10 %
(1 + a) T – 5
ns
(1 + a) T – 10
ns
Address float time
tFRA
0
ns
(referred to RDØ)
Address Æ data input time
tDAID VDD = +5.0 V ±10 %
(2.5 + a + n) T – 37 ns
(2.5 + a + n) T – 52 ns
ASTBØ Æ data input time
tDSTID VDD = +5.0 V ±10 %
(2 + n) T – 40 ns
(2 + n) T – 60 ns
RDØ Æ data input time
tDRID VDD = +5.0 V ±10 %
(1.5 + n) T – 50 ns
(1.5 + n) T – 70 ns
ASTBØ Æ RDØ delay time
tDSTR
0.5T – 9
ns
Data hold time
tHRID
0
ns
(referred to RD•)
RD• Æ address active time tDRA Upon program VDD = +5.0 V ±10 %
0.5T – 2
ns
read
0.5T – 12
ns
Upon data read VDD = +5.0 V ±10 %
1.5T – 2
ns
1.5T – 12
ns
RD• Æ ASTB• delay time
tDRST
0.5T – 9
ns
RD low-level width
tWRL
VDD = +5.0 V ±10 %
(1.5 + n) T – 30
ns
(1.5 + n) T – 40
ns
Address hold time
tHWA
0.5T – 14
ns
(referred to WR•)
Address Æ WRØ delay time tDAW VDD = +5.0 V ±10 %
(1 + a) T – 5
ns
(1 + a) T – 10
ns
ASTBØ Æ data output delay time tDSTOD VDD = +5.0 V ±10 %
0.5T + 15
ns
0.5T + 20
ns
ASTBØ Æ data output time
tDWOD
0.5T – 11
ns
ASTBØ Æ WRØ output delay time tDSTW
0.5T – 9
ns
Remark T: TCYK (system clock cycle time)
a: 1 when address wait is applied, 0 in other cases
n: number of wait cycles (n • 0)
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